1. Field of the Invention
The present invention relates to a regulator circuit capable of responding to a variation of a load current.
2. Description of the Related Art
An integrated circuit, such as a micro controller unit (MCU), equipped onto a semiconductor chip is sometimes configured such that a regulator circuit is also equipped onto the semiconductor chip and the regulator circuit supplies the integrated circuit with a voltage lower than an external power supply which is externally applied. The reasons include an inability of applying a high voltage to a digital circuit (i.e., an internal power supply voltage must be reduced) because a withstand voltage of elements constituting the circuit is reduced with miniaturization, and a suppression of a consumption power during operation and standby, et cetera. A representative example is a circuit reducing an internal power supply voltage to 1.8 volts from the external power supply voltage of 3.3 volts.
FIG. 1 shows a configuration of a regulator circuit according to a first conventional example. The circuit is one shown in FIG. 1 of “A Capacitor-Free CMOS Low-Dropout Regulator With Damping-Factor-Control Frequency Compensation” authored by K. N. Leung, et al; IEEE Journal of Solid-State Circuits, vol. 38, No. 10, p.p. 1691-1702; October 2003 (noted as “non-patent document 1” hereinafter). In the showing of FIG. 1 herein, an RF1 and RF2 are resistors, an AMP1 is an operational amplifier circuit, a GND is a ground (i.e., a ground terminal), a VCC is an external power supply voltage (e.g., 3.3 volts), an AMPO1 is an output signal of the operational amplifier circuit AMP1, an IB1 is a current source for generating a bias current, an MPB and MPP1 are P-channel MOS FET (noted as “PMOS transistor” hereinafter), a VDD is an internal power supply voltage, a COUT is a capacitor for stabilizing the internal power supply voltage, a DIVO1 is an output signal of a voltage division circuit constituted by the resistors RF1 and RF2, a PPG1 is a signal input to the gate of the PMOS transistor MPP1, and a Vbgr is a reference voltage applied to an inverting input terminal of the operational amplifier circuit AMP1. The component signs such as RF1 and RF2 are also used as symbols indicating characteristic values (e.g., a resistance value, capacitance value or voltage values) of elements. The similar terminologies are used hereinafter.
An output signal DIVO1 is input to a non-inverting input terminal of the operational amplifier circuit AMP1. By this, the operational amplifier circuit AMP1 outputs, to the gate of the PMOS transistor MPB, an output signal AMPO1 of a voltage according to the difference between a voltage value of the output signal DIVO1 and that of a reference voltage Vbgr. The PMOS transistor MPB and current source IB1 function as source follower circuit and outputs an output signal PPG1 which is shifted from a potential of the output signal AMPO1 by a potential equivalent to a threshold voltage (Vth) of the PMOS transistor MPB. The source follower circuit also functions as buffer circuit for driving a load capacitance of the PMOS transistor MPP1.
An external power supply voltage VCC is applied to the source of the PMOS transistor MPP1 and the drain thereof is connected to the resistor RF1 and the capacitor COUT. The other terminal of the capacitor COUT is connected to the ground GND, and a voltage across the terminals of the capacitor COUT is the internal power supply voltage VDD. The other terminal of the resistor RF1 is individually connected to the resistor RF2 and the non-inverting input terminal of the operational amplifier circuit AMP1, and the other terminal of the resistor RF2 is connected to the ground GND. By this, the division circuit outputs, as an output signal DIVO1, a signal obtained by dividing the internal power supply voltage VDD by the respective resistance values of the resistors RF1 and RF2, that is, a signal of a voltage value of VDD·RF2/(RF1+RF2).
The next is a specific description on an operation associated with a fluctuation of the internal power supply voltage VDD according to the above noted first conventional example.
With a fluctuation of the internal power supply voltage VDD, a voltage value of an output signal DIVO1 fluctuates. If a voltage value of the output signal DIVO1 becomes higher than a voltage value of the reference voltage Vbgr due to a fluctuation of the internal power supply voltage VDD, a voltage value of an output signal AMPO1 of the operational amplifier circuit AMP1 becomes large. As a result, a source potential of the PMOS transistor MPB, that is, a voltage value of a signal PPG1 input to the gate of the PMOS transistor MPP1, increases, resulting in decreasing a current flowing between the source and drain, and decreasing a potential of the internal power supply voltage VDD, which in turn decreases a potential of the output signal DIVO1.
Contrarily, if a voltage value of the output signal DIVO1 becomes lower than a voltage value of the reference voltage Vbgr due to a fluctuation of the internal power supply voltage VDD, a voltage value of an output signal AMPO1 of the operational amplifier circuit AMP1 becomes small. As a result, a voltage value of a signal PPG1 input to the gate of the PMOS transistor MPP1 decreases, resulting in increasing a current flowing between the source and drain, and increasing a potential of the internal power supply voltage VDD, which in turn increases a potential of the output signal DIVO1.
As such, the first conventional example comprises a feedback circuit for controlling a voltage value of the internal power supply voltage VDD so that a voltage value of the output signal DIVO1 is identical with that of a reference voltage Vbgr. This makes it possible to maintain the voltage value of the internal power supply voltage VDD at 1.8 volts if the reference voltage Vbgr has the voltage value of 1.2 volts and the resistors RF1 and RF2 of resistance values are adopted so that the voltage value of the output signal DIVO1 becomes two thirds (⅔) of that of the internal power supply voltage VDD.
The above noted feedback circuit is constituted by the entire circuit of the first conventional example, including the capacitor COUT in the feedback loop. This has caused a difficulty in maintaining a balance between a stability of the loop and a response characteristic for keeping track of potentials of the signals AMPO1 and PPG1 in high speed in response to a voltage fluctuation of the internal power supply voltage VDD.
FIG. 2 shows a configuration of a regulator circuit according to a second conventional example. The circuit is configured to maintain the stability and high speed response, which is shown in FIG. 3 of the non-patent document 1. In the showing of FIG. 2 herein, an RF1 and RF2 are resistors, an AMP1 is an operational amplifier circuit, an AMP2 and DFC are amplifier circuits for amplifying an input signal by being non-inverted, a DFCO is an output signal of the amplifier circuit DFC, a GND is a ground (i.e., a ground terminal), a VCC is an external power supply voltage, an AMPO1 is an output signal of the operational amplifier circuit AMP1, an MPP1 is a PMOS transistor, a VDD is an internal power supply voltage, a COUT is a capacitor for stabilizing the internal power supply voltage, a DIVO1 is an output signal of a voltage division circuit constituted by the resistors RF1 and RF2, a CF is a capacitor for adding a capacitance to the voltage division circuit, a CM1 and CM2 are capacitors for a phase compensation, a PPG1 is a signal input to the gate of the PMOS transistor MPP1, a Vbgr is a reference voltage applied to an inverting input terminal of the operational amplifier circuit AMP1.
The next is a specific description of an operation associated with a fluctuation of the internal power supply voltage VDD according to the above noted second conventional example.
The second conventional example is configured to have the amplifier circuit AMP2 amplify an output signal AMPO1 with the same polarity and input the amplified signal to the gate of the PMOS transistor MPP1 as a signal PPG1. This makes the individual signals AMPO1, PPG1, VDD and DIVO1 change approximately in the same manner as in the case of the first conventional example shown in FIG. 1 according to the relationship of a potential between the signals Vbgr and DIVO1. The function of a feedback circuit comprised by the second conventional example is for controlling a voltage value of the internal power supply voltage VDD so that a voltage value of the output signal DIVO1 is identical with that of the reference voltage Vbgr in the same manner as the first conventional example.
An expression representing a transfer characteristic of an open loop gain for the second conventional example results in including three poles since the three amplification stages, i.e., the operational amplifier circuit AMP1, amplifier circuit AMP2, and PMOS transistor MPP1, are serially connected with one another. Meanwhile, the feedback circuit comprises the resistors RF1 and RF2, and the capacitor CF. According to this, it is apparent that one zero-point created by the capacitor CF is included, when considering a transfer characteristic of the loop (i.e., the part from an input into the operational amplifier circuit AMP1 to an output of the signal DIVO1). A zero-point is also created by the capacitor COUT because an equivalent serial resistor component actually exists in the capacitor COUT which is disposed for stabilizing an internal power supply voltage VDD.
From the facts as described above, the transfer function overall includes three poles and two zero-points. Therefore, an appropriate cancellation of two zero-points and two poles with each other makes it possible to make a characteristic of the overall transfer function close to the one including one pole. In order to make two zero-points and two poles cancel with each other appropriately, the relationship between the two poles must be controlled so as to prevent an occurrence of a large peak in an amplitude characteristic on the frequency axis. The amplifier circuit DFC and capacitor CM2 are disposed for the control. The capacitor CM1 functions as mirror capacitance, accomplishing a phase compensation with the pole of the output signal AMPO1 of the operational amplifier circuit AMP1 being a dominant pole.
For the phase compensation, the control is to limit the capacitance value CM1, which makes the Dole of the output signal AMPO1 as the dominant pole, to a minimum value of necessity, and, as for the relationship of the two high-order poles, the control is in a manner to not generate a large peak in the amplitude characteristic by using the capacitor CM2 and amplifier circuit DFC. This configuration prevents the two poles from widely separating from each other on the frequency axis, thereby enabling an improvement of a high speed response. As a result, a stability of the loop and a high speed response thereof are both obtained in a balance.
The second conventional example intends to obtain both a high speed response (i.e., traceability) and a stability of a feedback loop in a balance in the case of a fluctuation of a load current, by devising a method of phase compensation. However, there is a limit in a balanced obtainment of a high speed response and stability because the second conventional example also includes a capacitor COUT for stabilizing the internal power supply voltage VDD in the feedback loop. Consequently, a trial has been attempted to obtain the balance by fundamentally reexamining a circuit configuration.
FIG. 3 shows a configuration of a regulator circuit according to a third conventional example. The circuit is for obtaining both stability and a high speed response by fundamentally reexamining the circuit configuration shown in FIG. 3 of “Area-Efficient Linear Regulator With Ultra-Fast Load Regulation”, authored by P. Hazucha, et al; IEEE Journal of Solid-State Circuits, vol. 40, No. 4, pp 933-940; April 2005 (noted as “non-patent document 2” hereinafter). In the showing of FIG. 3, an AMPF1 is a feedback control-use operational amplifier circuit, a Vset is an output signal of the operational amplifier circuit AMPF1, a Vref is a reference voltage applied to a non-inverting input terminal of the operational amplifier circuit AMPF1, an AMPLD1 is a load driving amplifier for generating an internal power supply voltage VDD, an AMPLD1R is a replica circuit (i.e., a replica amplifier) of the same configuration as the aforementioned load driving amplifier.
The load driving amplifier AMPLD1 comprises three PMOS transistors MP1, MPP1 and MPS and two N-channel MOF FETs (noted as “NMOS transistor” hereinafter) MN1 and MNB1. Respective sources of the PMOS transistors MP1 and MPP1 are applied by an external power supply voltage VCC, with the drain of the PMOS transistor MP1 being connected to the drain of the NMOS transistor MN1 and the gate of the PMOS transistor MPP1. A PPG1 is a signal input to the aforementioned gate. The source of the NMOS transistor MN1 is connected to the drain of the NMOS transistor MNB1, with the gate of the NMOS transistor MN1 being applied by the external power supply voltage VCC. The drain of the NMOS transistor MNB1 is additionally connected to the drain of the PMOS transistor MPS, and the source of the NMOS transistor MNB1 is connected to the ground GND. An NB1 is a signal input to the gate of the NMOS transistor MNB1. The source of the PMOS transistor MPS is connected to the drain of the PMOS transistor MPP1 and the capacitor COUT. The internal power supply voltage VDD is equivalent to the voltage across the terminals of the capacitor COUT.
For the replica amplifier AMPLD1R, which is the same configuration as the load driving amplifier AMPLD1, the elements constituting the former and the signals output from the elements are assigned by component signs which are added by “R” to the signs corresponding to the ones used for the load driving amplifier AMPLD1. For example, the MP1R is allocated as a sign to a PMOS transistor corresponding to the PMOS transistor MP1. As this defines the correlation, a detailed description is omitted. The inverting input terminal of the operational amplifier circuit AMPF1 is applied by a drain voltage VDDR (i.e., a replica internal power supply voltage VDD) of the PMOS transistor MPP1R, which is corresponded by the internal power supply voltage VDD. The output signal Vset of the operational amplifier circuit AMPF1 is input to the respective gates of the PMOS transistors MPS and MPSR.
The next is a specific description of an operation of the above described third conventional example.
In the third conventional example, the feedback circuit is constituted by the operational amplifier circuit AMPF1 and replica amplifier AMPLD1R. The feedback circuit functions so that a voltage value of a reference voltage Vref becomes identical with that of a drain voltage VDDR. For example, if the voltage value of the reference voltage Vref is 1.8 volts, that of the drain voltage VDDR becomes 1.8 volts.
If a voltage value of a drain voltage VDDR exceeds that of the reference voltage Vref, that of an output signal Vset of the operational amplifier circuit AMPF1 decreases, by which a current flowing between the source and drain of the PMOS transistor MPSR increases. Since a current flowing between the drain and source of the NMOS transistor MNB1R is of a constant volume determined by a signal NB1, however, a current flowing between the drain and source of the NMOS transistor MN1R decreases, which then causes a potential of the signal PPG1R to increase and therefore a current flowing between the source and drain of the PMOS transistor MPP1R decreases, lowering the drain voltage VDDR.
Contrarily, if a voltage value of the drain voltage VDDR becomes lower than that of the reference voltage Vref, a voltage value of an output signal Vset of the operational amplifier circuit AMPF1 increases, by which a current flowing between the source and drain of the PMOS transistor MPSR decreases. Since a current flowing between the drain and source of the NMOS transistor MNB1R is of a constant volume, however, a current flowing between the drain and source of the NMOS transistor MN1R increases, which then causes a potential of the signal PPG1R to decrease and therefore a current flowing between the source and drain of the PMOS transistor MPP1R increases, lifting the drain voltage VDDR.
The operation as described above is accomplished according to the relationship of magnitude of potentials between the drain voltage VDDR and reference voltage Vref, thereby being controlled so as to make these potentials identical. The replica amplifier AMPLD1R is configured the same as the load driving amplifier AMPLD1, and therefore the control results in maintaining the internal power supply voltage VDD at constant.
Note that characteristics of elements constituting the replica amplifier AMPLD1R may not necessarily be the same as those of elements constituting the load driving amplifier AMPLD1. For example, the current flowing in the load driving amplifier AMPLD1 may be controlled with designing the current of the replica amplifier AMPLD1R to be lower than that of the load driving amplifier AMPLD1.
Incidentally, although the internal power supply voltage VDD can be controlled to be completely identical with the drain voltage VDDR in the case of a load current not flowing, a load current according to an operation of an integrated circuit (i.e., a digital circuit) must be supplied. Accordingly, the next description is of an operation in the case of a load current flowing.
The load driving amplifier AMPLD1 increases a current flowing between the source and drain of the PMOS transistor MPP1 if a load current increases, while it decreases the current flowing between the source and drain thereof if the load current decreases. Therefore, the load driving amplifier AMPLD1 functions as feedback circuit. That is, the amplifier AMPLD1 comprises a feedback circuit for a load current.
As a load current increases, an internal power supply voltage VDD decreases. Since the reference voltage Vref is constant, a voltage between the gate and source of the PMOS transistor MPS decreases with the decrease of the internal power supply voltage VDD, and a current flowing between the drain and source thereof decreases. Since a current flowing between the drain and source of the NMOS transistor MNB1 is constant, a decrease of the current flowing between the drain and source of the PMOS transistor MPS causes a current flowing between the drain and source of the NMOS transistor MN1 to increase, which then decreases a potential of the signal PPG1, resulting in increasing a current flowing between the source and drain of the PMOS transistor MPP1.
Contrarily, if a load current decreases, an internal power supply voltage VDD increases. Since the reference voltage Vref is constant, a voltage between the gate and source of the PMOS transistor MPS increases with the increase of the internal power supply voltage VDD, the current flowing between the drain and source thereof increases. Since a current flowing between the drain and source of the NMOS transistor MNB1 is constant, the increase of the current flowing between the drain and source of the PMOS transistor MPS causes a current flowing between the drain and source of the NMOS transistor MN1 to decrease, which then increases a potential of the signal PPG1, resulting in decreasing a current flowing between the source and drain of the PMOS transistor MPP1.
As such, the load driving amplifier AMPLD1 comprises a feedback function for increasing or decreasing the current flowing between the source and drain of the PMOS transistor MPP1 in response to an increase or decrease of the load current. Due to this, even if a design is such as to make a drain voltage VDDR and an internal power supply voltage VDD identical in the case of a load current not flowing, a difference of potentials (noted as “potential difference” hereinafter) between the aforementioned two voltages is generated when a load current flows. Such a potential difference is determined by the magnitude of a load current and the amplification ratio of the load driving amplifier AMPLD1.
For the above described second conventional example, a gain of the feedback loop is determined by the product of the respective amplification ratios of the operational amplifier circuit AMP1, amplifier circuit AMP2 and PMOS transistor MPP1. This accordingly requires a design for a large gain so as to prevent a large fluctuation of a voltage value of the internal power supply voltage VDD caused by variations of temperature, external power supply voltage VCC, production process or load current.
Comparably, in the third conventional example, the feedback circuit for suppressing a change in a voltage value of an internal power supply voltage VDD is constituted by the operational amplifier circuit AMPF1 and replica amplifier AMPLD1R. Therefore, it is good enough if a gain calculated by the product of those amplification ratios is adequate. Therefore, it is possible to control so as to make the respective voltage values of a drain voltage VDDR and an internal power supply voltage VDD constant by setting a voltage value of an output signal Vset.
The function for controlling a voltage value of the internal power supply voltage VDD so as to be constant in the case of a load current fluctuating is comprised by only the load driving amplifier AMPLD1. Because of this, a gain required at the load driving amplifier AMPLD1 is adequate if it is capable of keeping a variation of the internal power supply voltage VDD within a desired range in response to a fluctuation of a load current. Therefore, it is adequate if a smaller gain than one required for the second conventional example is accomplished. A gain to be accomplished may be relatively small, with being able to suppress a variation of a voltage value of the internal power supply voltage VDD to a certain degree against a fluctuation of the load current. A capacitor COOT is connected to such a load driving amplifier AMPLD1. As a result of these, considering that a frequency in which a gain becomes 0 dB is constant, the load driving amplifier AMPLD1 is capable of easily accomplishing a wider band and a higher speed response by taking advantage of a small gain of the amplifier AMPLD1.
According to the aspects as described above, the third conventional example is configured to separate a feedback circuit responding to fluctuations of temperature, external power supply voltage VCC and production process from a feedback circuit responding to a fluctuation of a load current. By this, stability and a high speed response are balanced by accomplishing a high speed response more easily.
The third conventional example shown in FIG. 3 is configured in a manner to make potentials of an internal power supply voltage VDD and of a reference voltage Vref identical. This accordingly requires a reference voltage Vref of 1.8 volts in the case of controlling the internal power supply voltage VDD at 1.8 volts for example.
A reference voltage is commonly generated by using a bandgap circuit. FIGS. 4 and 5 show representative bandgap circuits. Such circuits are noted in “A CMOS Bandgap Reference Circuit with Sub-1-V Operation”, authored by H. Banba, et al; IEEE Journal of Solid-State Circuits, vol. 34, No. 5, pp 670-674, May 1999 (noted as “non-patent document 3” hereinafter) Accordingly, a specific description at this point is on the representative bandgap circuit by referring to FIGS. 4 and 5.
The bandgap circuit is configured to add a potential of a forward-biased p-n junction and a voltage (i.e., PTAT voltage) which is Proportional To Absolute Temperature (PTAT), thereby obtaining a reference voltage independent of a temperature. A potential of a p-n junction is known as Complementary To Absolute Temperature (CTAT; a negative linear dependency to an absolute temperature T) if the potential is approximated by a linear expression, or within a range that such approximation by a linear expression is appropriate. Because of this, a reference voltage approximately independent of a temperature can be obtained by adding an appropriate PTAT voltage to a potential of a p-n junction.
FIG. 4 shows a configuration of a first bandgap circuit. In the showing of FIG. 4, a Q1 and Q2 are pnp bipolar transistor (noted as “pnp transistor” hereinafter), an R1 through R5 are resistors, an AMP3 and AMP4 are operational amplifier circuits, a GND is the ground, a Vbgr is a bandgap voltage, a Vref is a reference voltage, an IAM and IAP are internal nodes, a DIVO2 is an output signal of a voltage division circuit constituted by the resistors R4 and R5. An “x1” and “x10” attached to the pnp transistors Q1 and Q2, respectively, indicate a relative ratio of areas between them, that is, an area size of the transistor Q1 is one tenths of that of the transistor Q2.
The next description is of an operation thereof.
Using Vbe to express a voltage across the base and emitter of a bipolar transistor, or a forward voltage of a p-n junction, the relationship between the forward voltage and an absolute temperature T is known to be expressed by:Vbe=Veg−a·T  (1);
where Veg is a bandgap voltage (i.e., approximately 1.2 volts) of silicon; and “a” is a coefficient expressing temperature dependence of a bandgap voltage Veg. The temperature dependence is known to be approximately 2 mV/° C. in a practical range although it is dependent on a bias current.
A rough relationship between an emitter current IE and a forward voltage Vbe of the bipolar transistor is known as follows:IE=IOexp(q·Vbe/k·T)  (2);
where IO is a constant proportional to area size, q is a charge of an electron, and k is the Boltzmann constant. If the gain is adequately large by a feedback of the operational amplifier circuit AMP3, the potentials of signals respectively input by way of the nodes IAN and IAP are (approximately) equal, thus stabilizing the circuit. In this event, if the ratio of resistance values of the resistors R1 to R2 is designed as one to ten (1:10) for example, the ratio of magnitudes of currents flowing in the pnp transistors Q1 to Q2 becomes ten to one (10:1). Therefore, the magnitudes of currents flowing in the transistors Q1 and Q2 are respectively expressed by 10xI and I for convenience here. Mentioned “x1” and “x10” in FIG. 4 shows the ratio of relative area between the transistors Q1 and Q2.
Where expressing Vbe1 and Vbe2 for voltages between the respective bases and emitters of the pnp transistors Q1 and Q2, a relationship is derived from the expression (2), as follows:10xI=IOexp(q·Vbe1/k·T)  (3)I=10·IOexp(q·Vbe2/k·T)  (4)
Summarizing the expressions by a division on either side, respectively, obtains the following expression (5), and summarizing by expressing Vbe1−Vbe2=ΔVbe obtains the following expression (6):100=exp(q·Vbe1/k·T−q·Vbe2/k·T)  (5)ΔVbe=(k·T/q)ln(100)  (6)
As apparent from the expression (6), the ΔVbe, i.e., the difference of voltages between the respective bases and emitters of the pnp transistors Q1 and Q2, is expressed by a natural logarithm (=ln (100)) of a current density ratio (=100) of the transistors Q1 and Q2 and a thermal voltage (k·T/q). Because the voltage difference ΔVbe is equal to a potential difference between both of the terminals of the resistor R3, a current of ΔVbe/R3 flows in the resistors R2 and R3. Therefore, a potential difference VR2 between both of the terminals of the resistor R2 is expressed as follows:VR2=ΔVbe·R2/R3  (7)
The respective potentials of the nodes IAP and IAM are equal to the voltage Vbe1, and therefore a bandgap voltage Vbgr is represented by the following expression:Vbgr=Vbe1+ΔVbe·R2/R3  (8)
The forward voltage Vbe1 has a negative temperature dependence decreasing with temperature increase (refer to the expression (1)) and the voltage difference ΔVbe increases proportionately with temperature as shown by the expression (6) Because of this, it is possible to design so that a voltage value of a bandgap voltage Vbgr is independent of a temperature by selecting a constant appropriately. The voltage value results in approximately 1.2 volts which is equivalent to the bandgap voltage of silicon.
The reference voltage Vref of 1.8 volts can be generated by setting the bandgap voltage Vbgr 1.5 times thereof. Setting the resistance ratio of R4 to R5 constituting the voltage division circuit at one to two (1:2), the potential of a reference voltage Vref is determined so as to equalize the potentials of an output signal DIVO2 and of a bandgap voltage Vbgr, thereby making it possible to generate the reference voltage Vref of 1.8 volts. The third conventional example shown in FIG. 3 generates an internal power supply voltage VDD of 1.8 volts by applying such a reference voltage Vref to the non-inverting input terminal of the operational amplifier circuit AMPF1.
In the case of making the operational amplifier circuit AMP4 perform an arithmetic operation of magnifying a bandgap voltage Vbgr 1.5 times, in practice, a voltage error caused by an offset of the operational amplifier circuit AMP4 influences on a voltage accuracy of a reference voltage Vref in addition to generation accuracy of the bandgap voltage Vbgr. That is, the reference voltage Vref contains an error caused by a circuit part for generating the reference voltage Vref from the bandgap voltage Vbgr, and the error consequently degrades voltage accuracy of an internal power supply voltage VDD. That is, a combination of the conventional circuit shown in FIG. 3 with a bandgap circuit such as the one shown in FIG. 4 is faced with a problem of an error caused by the operational amplifier circuit AMP4 shown in FIG. 4 being added to the reference voltage Vref.
FIG. 5 shows a configuration of a second bandgap circuit which is a circuit called as a bandgap circuit of an electric current mode and is capable of generating a discretionary reference voltage Vref, unlike the one shown in FIG. 4. In the showing of FIG. 5, an AMP5 is an operational amplifier circuit, an AMPO5 is an output signal of the operational amplifier circuit AMP5, an R6 through R8 are resistors, an MP2 through MP4 are PMOS transistors, and an IAM and IAP are internal nodes. The other signs are the same as in the case of FIG. 4.
The next description is of an operation thereof.
The bandgap circuit shown in FIG. 5 stabilizes potentials of the nodes IAM and IAP by being (approximately) equal to each other by a feedback of the operational amplifier circuit AMP5 in the same manner as the one shown in FIG. 4. Here, the assumption is that the sizes of the PMOS transistors MP2 and MP3 are the same, that is, currents of the same magnitude flow in them for simplicity of description. Also, likewise FIG. 4, an emitter area size of the pnp transistor Q2 is ten times that of the pnp transistor Q1. Also, voltages between the respective bases and emitters of the pnp transistors Q1 and Q2 are indicated by Vbe1 and Vbe2, respectively.
From the expression (2), there are apparently relationships in the bandgap circuit as follows:I=IOexp(q·Vbe1/k·T)  (9)I=10·IOexp(q·Vbe2/k·T)  (10)
Summarizing the expressions by dividing on either side obtains the expression (11), followed by summarizing it by expressing Vbe1−Vbe2=ΔVbe, thus obtaining the expression (12):10=exp(q·Vbe1/k·T−q·Vbe2/k·T  (11)ΔVbe=(k·T/q)ln(10)  (12)
As apparent from the expression (12), the difference ΔVbe of voltages between the respective bases and emitters of the pnp transistors Q1 and Q2 is expressed by a natural logarithm (=ln(10)) of an electric current density ratio (=10) of the transistors Q1 and Q2 and a thermal voltage (k·T/g). Because the voltage difference ΔVbe is equal to a potential difference between both of the terminals of the resistor R3, a current of ΔVbe/R3 flows in the resistor R3. Therefore, a current IR3 flowing in the resistor R3 is expressed as follows:IR3=ΔVbe/R3  (13)
The respective potential of the nodes IAP and IAM are equal to the Vbe1, and therefore resistors of the same resistance value are selected for the resistors R6 and R7. Assuming the resistance value as R67, and the current flowing in the individual resistors as IR67, the current IR67 is expressed as follows:IR67=Vbe1/R67  (14)
Since the sizes of the PMOS transistors MP2 and MP3 are assumed to be the same for simplicity of description herein, the currents flowing in individual transistors MP2 and MP3 are sum of the currents calculated by the expressions (13) and (14) respectively. Therefore, the current, defined as IMP23, is represented by the following expressions:IMP23=ΔVbe/R3+Vbe1/R67  (15)
The forward voltage Vbe1 has negative temperature dependence that decreases with temperature increase (refer to the expression (1)), and the voltage difference ΔVbe increases proportionately with temperature as shown by the expression (12). Therefore, an appropriate selection of a constant enables a design so as to make a current value of the current IMP23 flowing in the PMOS transistors MP2 and MP3 become independent of a temperature. A reference voltage Vref independent of a temperature can be generated by having the same current equivalent to the current IMP23 in the resistor R8. Assuming that all the sizes of the PMOS transistors MP2 through MP4 are the same, with the same magnitude of current flowing in them, the reference voltage Vref is represented by the following expression:Vref=(ΔVbe/R3+Vbe1/R67)·R8  (16)
As apparent from the expression (16), a voltage value of the reference voltage Vref can be discretionarily selected by a resistance value of the resistor R8. Therefore, it is possible to generate a reference voltage Vref of a discretionary voltage value directly without using an operational amplifier circuit.
For the bandgap circuit shown in FIG. 4, a ratio of currents flowing in the pop transistors Q1 to Q2 is designed by a ratio of resistance of the resistors R1 to R2. Comparably, for the bandgap circuit shown in FIG. 5, the ratio of currents is designed by an area size ratio of the PMOS transistors MP2 to MP3, and also a value of the current flowing in the resistor R8 is designed by an area size ratio of the PMOS transistor MP4 to PMOS transistor MP2 (or MP3). This causes a voltage error of the reference voltage Vref to increase by a mismatch among the PMOS transistors MP2, MP3 and MP4. That is, a case of combining the conventional circuit shown in FIG. 3 with a bandgap circuit as shown in FIG. 5 is also faced with the problem of adding an error caused by a mismatch among the PMOS transistors MP2, MP3 and MP4 to a reference voltage. Comparing accuracy of matching resistors with that of matching MOS transistors, the former is generally expected to be better. This is because a resistance value is determined by its dimensions and impurity concentration or dose of a resistor, whereas other parameters to be controlled exist, such as an oxide film thickness, in addition to a form and a concentration of impurities of a channel for the MOS transistors. Because of this, the voltage accuracy of a reference voltage Vref is generally higher with the bandgap circuit shown in FIG. 4.
As described above, an error is included in a reference voltage Vref generated by a bandgap circuit. The error degrades voltage accuracy of an internal power supply voltage VDD. Accordingly conceivable is to avoid an influence of the error by using a bandgap voltage Vbgr directly.
FIG. 6 shows a configuration of a regulator circuit according to a modified example of the third conventional example. The modified example is configured to supply a non-inverting input terminal of the operational amplifier circuit AMPF1 with a bandgap voltage Vbgr as a reference voltage. Resistors RF1R and RF2R are connected between the drain of a PMOS transistor MPP1R and ground GND. The inverting input terminal of the operational amplifier circuit AMPF1 is connected to the other terminal of the resistor RF1R. By this, the inverting input terminal is input by an output signal DIVO1R of a voltage division circuit which is constituted by the resistors RF1R and RF2R.
The third conventional example shown in FIG. 3 is configured to generate an internal power supply voltage VDD of 1.8 volts. Therefore, a drain voltage VDDR is usually 1.8 volts. A bandgap voltage is 1.2 volts. Because of this, the resistance ratio of the resistors RF1R and RF2R constituting the above described voltage division circuit is designed as RF1R:RF2R=1:2. By this, the voltage division circuit divides the drain voltage VDDR and outputs an output signal DIVO1R of 1.2 volts. Since such an output signal DIVO1R is supplied to the inverting input terminal of the operational amplifier circuit AMPF1, a bandgap voltage Vbgr of 1.2 volts can be used as is.
The third conventional example shown in FIG. 3 and the modified example thereof shown in FIG. 6 comprise only one load driving amplifier AMPLD1. There is, however, a case in which a plurality of such amplifiers AMPLD1 is desired to be furnished. The reason is that there is a case of dividing an integrated circuit on a semiconductor chip into a circuit part, such as a register and memory, which is to be supplied with a power supply voltage at all times, and a circuit part from which the power supply voltage is shut off except at the time of an operation. In such a case, the same number of load driving amplifiers as the number of divided circuit parts is usually furnished.
In the case of furnishing a plurality of power supply circuits such as the load driving amplifier AMPLD1, the power supply circuits are desirably to be placed close to circuits (i.e., digital circuits) constituting loads from a view point of minimizing an internal power supply line length. As a result, the third conventional example shown in FIG. 3 (and the modified example thereof shown in FIG. 6) places the load driving amplifier AMPLD1 and replica amplifier AMPLD1R apart from each other in many cases.
The third conventional example requires characteristics of the PMOS transistors MPS and MPSR to be identical to each other highly accurately in order to generate an internal power supply voltage VDD in high accuracy. As widely known, a characteristic of element produced onto a semiconductor chip by the production process is affected by a position on the semiconductor chip and a layout of the surrounding area. Therefore, a physical closeness is very important in order to make the characteristics of the elements identical in high accuracy. Consequently, if the load driving amplifier AMPLD1 and replica amplifier AMPLD1R are placed far apart from each other, it becomes difficult to make the characteristics of the PMOS transistors MPS and MPSR identical in high accuracy.
Consequently, an internal power supply voltage VDD cannot always be securely generated in high accuracy even if the bandgap voltage Vbgr is used as a reference voltage as in the modified example shown by FIG. 6. Accordingly, having been required is a capability of generating an internal power supply voltage VDD securely in high accuracy. Also required strongly is a capability of generating such an internal power supply voltage by a simpler configuration. That is, there has been a problem of an error caused by a mismatch of the PMOS transistors MPS and MPSR being added to a generated power supply voltage if the physical distance between the PMOS transistors MPS and MPSR becomes large even in the case of adopting a circuit as shown in FIG. 6.
The reference technical documents include U.S. Pat. Nos. 6,285,246; 6,300,749; 6,388,433; 6,847,260; 6,175,223; Laid-Open Japanese Patent Application Publication Nos. 08-272461, 2005-202781, 2004-152891, 2002-157031, Japanese Translation of PCT International Application Publication No. 2004-504660, and Laid-Open Japanese Patent Application Publication No. 2005-276190.